There are two general schemes for integrating a Field Effect Transistor (FET) into a semiconductor substrate: horizontal and vertical integration. In horizontal integration, carrier flow in the field effect transistor, from source to drain, occurs in the direction parallel to the plane of the substrate, i.e. parallel to the top and bottom faces of the substrate. In contrast, in a vertical FET, current flow from the source to the drain occurs transverse to the plane of the substrate, i.e. transverse to the top and bottom faces of the substrate.
Horizontal FETs are widely used because of the relative ease of isolation among devices, and because of the ease of application to large scale integration. Large scale integration is more easily implemented with horizontal FETs because the drain, source and gate contacts are all located on one face of the substrate. Vertical FETs, on the other hand, generally have a superior power-delay product and a higher power handling capacity compared with their lateral counterparts. Moreover, for high power devices, the provision of a source contact on one substrate face and a drain contact on the opposite substrate face maximizes power handling ability.
In view of these advantages, much development effort has been focused on vertical field effect transistors in silicon and gallium arsenide. Silicon based vertical field effect transistors are described in publications entitled A Vertical FET With Self-Aligned Ion-Implanted Source and Gate Regions by Ozawa et al., IEEE Transactions on Electron Devices, Vol. ED-25, No. 1, January 1978, pp. 56-57; Proposed Vertical-Type Amorphous-Silicon Field-Effect Transistors by Uchida, IEEE Electron Device Letters, Vol. EDL-5, No. 4, April 1984, pp. 105-107; Vertical-Type Amorphous-Silicon Field-Effect Transistors with Small Parasitic Elements by Uchida et al., Japanese Journal of Applied Physics, Vol. 25, No. 9, September 1986, pp. L798-L800; A High-Power High-Gain VD-MOSFET Operating at 900 MHz by Ishikawa et al., IEEE Transaction on Electron Devices, Vol. ED-34, No. 5, May 1987, pp. 1157-1162; and Complementary Vertical Bipolar Transistor Process Using High-Energy Ion Implantation by Ragay et al., Electronics Letters, Vol. 27, No. 23, November 1991, pp. 2141-2143.
Gallium arsenide based vertical field effect transistors are described in U.S. Pat. No. 4,903,089 to Hollis et al. entitled Vertical Transistor Device Fabricated With Semiconductor Regrowth, and in publications entitled Ion-Implanted FET for Power Applications by Lecrosnier et al., Transactions on Electron Devices, Vol. ED-21, No. 1, January 1974, pp. 113-118; Semiconductors for High-Voltage, Vertical Channel Field Effect Transistors by B. J. Baliga, J. Appl. Phys. 53(3), March 1982, pp. 1759-1764; Vertical FET's in GaAs by Rav-Noy et al., IEEE Electron Device Letters, Vol. EDL-5, No. 7, July 1984, pp. 228-230; Vertical Field-Effect Transistors in III-V Semiconductors by Rav-Noy et al., Appl. Phys. Let. 45(3), August 1984, pp. 258-260; A Numerical Analysis of a Short Vertical n.sup.+ -n.sup.- -n.sup.+ GaAs MESFET by Lyden et al., IEEE Electron Device Letters, Vol. EDL-5, No. 2, February 1984, pp. 43-44; Vertical Integration of GaAs/AlGaAs Laser Diode and Vertical JFET by Yoo et al., Japanese Journal of Applied Physics, Vol. 27, No. 3, March 1988, pp. L431-L433; Determination of Electron Energy Distribution in a GaAs Vertical Field-Effect Transistor With Hot-Electron Injection by Yamasaki et al., Appl. Phys. Lett. 54(3), January 1989, pp. 274-276; A Vertical Integration of GaAs/GaAlAs LED and Vertical FET With Embedded Schottky Electrodes by Hong et al., Japanese Journal of Applied Physics, Vol. 29, No. 12, December 1990, pp. L2427-L2429; and A High Voltage-Gain GaAs Vertical Field-Effect Transistor With an InGaAs/GaAs Planar-Doped Barrier Launcher by Won et al, IEEE Electron Device Letters, Vol. 11, No. 9, September 1990, pp. 376-378.
Diamond is a preferred material for semiconductor devices because it has semiconductor properties that are better than silicon, germanium or gallium arsenide. Diamond provides a higher energy bandgap, a higher breakdown voltage and a higher saturation velocity than these traditional semiconductor materials.
These properties of diamond yield a substantial increase in projected cutoff frequency and maximum operating voltage compared to devices fabricated using silicon, germanium or gallium arsenide. Silicon is typically not used at temperatures higher than about 200.degree. C. and gallium arsenide is not typically used above 300.degree. C. These temperature limitations are caused, in part, because of the relatively small energy band gaps for silicon (1.12 eV at ambient temperature) and gallium arsenide (1.42 eV at ambient temperature). Diamond, in contrast, has a large band gap of 5.47 eV at ambient temperature, and is thermally stable up to about 1400.degree. C.
Diamond has the highest thermal conductivity of any solid at room temperature and exhibits good thermal conductivity over a wide temperature range. The high thermal conductivity of diamond may be advantageously used to remove waste heat from an integrated circuit, particularly as integration densities increase. In addition, diamond has a smaller neutron cross-section which reduces its degradation in radioactive environments, i.e., diamond is a "radiation-hard" material.
Because of the advantages of diamond as a material for semiconductor devices, there is at present an interest in the growth and use of diamond for high temperature and radiation-hardened electronic devices. Since FETs are fundamental building blocks of modern integrated circuits, there is interest in the design and fabrication of diamond FETs.
The design and fabrication of horizontal diamond FETs have been widely reported in the art. See for example, U.S. Pat. No. 3,603,848 entitled Complementary Field-Effect-Type Semiconductor Device by Sato et al. and publications entitled High-Temperature Thin-Film Diamond Field-Effect Transistor Fabricated Using a Selective Growth Method by Gildenblat et al., IEEE Electron Device Letters, Vol. 12, No. 2, February 1991, pp. 37-39; Fabrication of an Insulated Gate Diamond FET for High Temperature Applications by Hewett et al., presented at the International High Temperature Electronics Conference in Albuquerque, NM, June 1991, pp. 168-173; IGFET Fabrication of Homoepitaxial Diamond Using in Situ Boron and Lithium Doping by Fountain et al., presented at the Electrochemical Society meeting held in Washington, DC in May, 1991; and Diamond MESFET Using Ultrashallow RTP Boron Doping by Tsai et al., IEEE Electron Device Letters, Vol. 12, No. 4, April 1991, pp. 157-159. See also the publication by A. J. Tessmer, K. Das and D. L. Dreifus entitled Polycrystalline Diamond Field-Effect Transistors, Diamond and Related Materials I (1992), pp. 89-92, Elsevier Science Publishers B.V., Amsterdam, Holland.
Development of vertical diamond FETs has not been as widely reported or as successful. A proposed diamond vertical FET structure is described in a publication entitled Diamond Transistor Performance and Fabrication by Geis, Proceedings of the IEEE, Vol. 79, No. 5, May 1991, pp. 669-676. Described at FIGS. 2 and 3 is a possible vertical field effect transistor formed on a conducting diamond substrate and having a bottom drain contact thereon, and a homoepitaxial boron doped diamond layer including gate and source regions. The publication notes, at page 670, that "at present, the technical problems in manufacturing a highly conductive diamond substrate have not been solved . . . ". See also an earlier publication by Geis et al. entitled Device Applications of Diamonds, Journal of Vacuum Society Technology, Vol. A6, No. 3, May-June 1988, pp. 1953-1954.
In conclusion, although vertical diamond field effect transistors are highly desirable, the art has not heretofore suggested a viable vertical diamond field effect transistor structure, or manufacturing process therefor.